The present invention concerns the field of semiconductor wafer fabrication. Specifically, it relates to the correction of proximity effects in patterning.
A. Wafer Construction
Photolithography is a common technique employed in the manufacture of semiconductor devices. Typically, a semiconductor wafer is coated with a layer (film) of light-sensitive material, such as photoresist. Using a patterned mask or reticle, the wafer is exposed to projected light, typically actinic light, which manifests a photochemical effect on the photoresist, which is subsequently chemically etched, leaving a pattern of photoresist xe2x80x9clinesxe2x80x9d on the wafer corresponding to the pattern on the mask.
A xe2x80x9cwaferxe2x80x9d is a thin piece of semiconductor material from which semiconductor chips are made. The four basic operations utilized to fabricate wafers include (1) layering, (2) patterning, (3) doping and (4) heat treatments.
The layering operation adds thin layers of material, including insulators, semiconductors, and conductors, to a wafer surface. During the layering operation, layers are either grown or deposited. Oxidation involves growing a silicon dioxide (an insulator) layer on a silicon wafer. Deposition techniques include, for example, chemical vapor deposition, evaporation, and sputtering. Semiconductors are generally deposited by chemical vapor deposition, while conductors are generally deposited with evaporation or sputtering.
Patterning involves the removal of selected portions of surface layers. After material is removed, the wafer surface has a pattern. The material removed may form a hole or an island. The process of patterning is also known to those skilled in the relevant art as microlithography, photolithography, photomasking and masking. The patterning operation serves to create parts of the semiconductor device on the wafer surface in the dimensions required by the circuit design and to locate the parts in their proper location on the wafer surface.
Doping involves implanting dopants in the surface of the wafer through openings in the layers to create the n-type and p-type pockets needed to form the N-P junctions for operation of discrete elements such as transistors and diodes. Doping is generally achieved with thermal diffusion (wafer is heated and exposed to the desired dopant) and ion implantation (dopant atoms are ionized, accelerated to high velocities and implanted into the wafer surface).
Construction of semiconductor wafers with these steps is well known in the art of semiconductor fabrication. Examples of wafer construction processes are described in U.S. Pat. No. 5,679,598 issued to Yee on Oct. 21, 1997, entitled xe2x80x9cMethod of Making a CMOS Dynamic Random-Access Memory (DRAM),xe2x80x9d U.S. Pat. No. 5,663,076 issued to Rostoker et al. on Sep. 2, 1997, entitled xe2x80x9cAutomating Photolithography in the Fabrication of Integrated Circuits,xe2x80x9d U.S. Pat. No. 5,595,861 issued to Garza on Jan. 21, 1997, entitled xe2x80x9cMethod of Selecting and Applying a Top Antireflective Coating of a Partially Fluorinated Compound,xe2x80x9d U.S. Pat. No. 5,444,265 issued to Hamilton on Aug. 22, 1995, entitled xe2x80x9cMethod and Apparatus for Detecting Defective Semiconductor Wafers During Fabrication Thereof,xe2x80x9d and U.S. Pat. No. 4,652,134 issued to Pasch et al. on Mar. 24, 1987, entitled xe2x80x9cMask Alignment System. xe2x80x9d The specifications of these five patents identified in this paragraph are hereby incorporated herein as though set forth in full by this reference.
B. Patterning And Proximity Effects
As the most critical operation of wafer fabrication, patterning sets the critical dimensions of the particular semiconductor device. Errors in the patterning process can cause distortions that cause changes in the function of the semiconductor device.
Design rule limitations are frequently referred to as critical dimensions. A critical dimension of a circuit is commonly defined as the smallest width of a line or the smallest space between two lines. Consequently, the critical dimension determines the overall size and density of an integrated circuit (IC). In present IC technology, the smallest critical dimension for state-of-the-art circuits is 0.3 micron for line widths and spacings. Once the layout of the circuit has been created, the next step to manufacturing the integrated circuit is to transfer the layout onto a semiconductor substrate. Photolithography is a well known process for transferring geometric shapes present on a mask onto the surface of a silicon wafer. In the field of IC lithographic processing a photosensitive polymer film called photoresist is normally applied to a silicon substrate wafer and then allowed to dry. An exposure tool is utilized to expose the wafer with the proper geometrical patterns through a mask (or reticle) by means of a source of light or radiation. After exposure, the wafer is treated to develop the mask images transferred to the photosensitive material. These masking patterns are then used to create the device features of the circuit.
An important limiting characteristic of the exposure tool is its resolution value. The resolution for an exposure tool is defined as the minimum feature that the exposure tool can repeatedly expose onto the wafer. Currently, the resolution for most advanced optical exposure tools is around 0.2 micron. Thus, the resolution value of present lithographic equipment is close to the critical dimension for most IC circuit designs. Consequently, the resolution of the exposure tool may influence the final size and density of the IC circuit. As the critical dimensions of the layout becomes smaller and approach the resolution value of the lithography equipment, the consistency between the masked and actual layout pattern developed in the photoresist is significantly reduced. Specifically, it is observed that differences in pattern development of circuit features depends upon the proximity of the features to one another.
The magnitude of such proximity effects depends on the proximity or closeness of the two features present on the masking pattern. Proximity effects are known to result from optical diffraction in the projection system. This diffraction causes adjacent features to interact with one another in such a way to produce pattern-dependent variations.
Proximity effects and methods for correcting for them are discussed in U.S. Pat. No. 5,682,323 issued on Oct. 28, 1997, to Pasch et al. entitled xe2x80x9cSystem and Method for Performing Optical Proximity Correction on Macrocell Librariesxe2x80x9d (hereinafter the xe2x80x9cPasch ""323 patentxe2x80x9d). The specification of the Pasch ""323 patent is incorporated herein as though set forth in full by this reference. The system and method described in the Pasch ""323 patent performs optical proximity correction on an integrated circuit mask design by initially performing optical proximity correction on a library of cells that are used to create the IC. The pre-tested cells are imported onto a mask design. All cells are placed a minimum distance apart to ensure that no proximity effects will occur between elements fully integrated in different cells. An optical proximity correction technique is performed on the mask design by performing proximity correction only on those components, e.g.,lines, that are not fully integrated within one cell.
Proximity effects and methods for correcting for them are also discussed in U.S. Pat. No. 5,705,301 issued on Jan. 6, 1998, to Garza et al. entitled xe2x80x9cPerforming Optical Proximity Correction with the Aid of Design Rule Checkersxe2x80x9d (hereinafter the xe2x80x9cGarza ""301 patentxe2x80x9d). The specification of the Garza ""301 patent is incorporated herein as though set forth in full by this reference. The system described in the Garza ""301 patent involves a method for identifying regions of an integrated circuit layout design where optical proximity correction will be most useful and then performing optical proximity correction on those regions only.
More specifically, the method includes the following steps: (a) analyzing an integrated circuit layout design with a design role checker to locate features of the integrated circuit layout design meeting predefined criteria; and (b) performing optical proximity correction on the features meeting the criteria in order to generate a reticle design. The criteria employed by the design rule checker to select features include outside corners on patterns, inside corners on features, feature size, feature shape, and feature angles.
C. Proximity Effect Correction
A technique related to proximity effects involves the use of modified shapes or adjacent subresolution geometries to improve imaging. An example of this is the use of serifs on the corners of contacts. FIGS. 1A and 1B show contacts as formed on a reticle. FIG. 1A shows a contact 1 without serifs. FIG. 1B shows the same contact 2 with serifs. For contacts with dimensions near the resolution limit of the optics, a square pattern on the reticle will print more nearly as a circle. Additional geometries on the corners such as those shown in FIG. 1B will help to square the corners of the contract. Techniques such as those reflected by FIGS. 1A and 1B are often called proximity correction.
In addition for corner rounding for rectangular features, there is also the issue of line shortening. FIG. 2A shows a rectangle 3 as drawn on a reticle with a width W and a length L. Printed to size on the wafer as shown in FIG. 2B, the rectangle has a length Lxe2x80x2 and width Wxe2x80x2 4. Where there is room, rectangles can be biased longer on the reticle to give printed features of the desired length.
FIG. 3A shows a conventional pattern 5 and FIG. 3B shows a corresponding proximity correction pattern 6 wherein width variation 7 has been added to compensate for effects of adjacent features and serifs 8 have been added to corners to reduce corner rounding and feature length shortening.
Other examples of proximity effects and the adjustments made to patterns in order to correct for such effects are provided in the Garza ""301 patent discussed above. In particular, FIGS. 1A, 1B, 1C, 1D, 2A, 5, 5A, 5B, 5C, 5D, 6, 7A, 7B, 7C, and 8 of the Garza ""301 patent provide such examples.
Proximity effects are a well-known phenomenon in electron beam lithography, where they result from electron scattering. In optical lithography proximity effects are caused by the phenomenon of diffraction. As a consequence of proximity effects, printed features do not have simple relationships to reticle dimensions. This creates a situation in which it is difficult to fabricate a photomask where the designer gets what he or she wants on the wafer. Unless otherwise expressly indicated in a claim herein, it is intended that the claimed invention can be applied to correct for proximity effects whether the proximity effects are optical, electron beam, x-ray or otherwise.
Some limited form of proximity correction has been in use for at least two or three decades. These pattern modifications were usually requested by a wafer engineer based on knowledge of a particular process step. In recent years, proximity correction has become more of a science that an art due to the introduction of several proximity correction software programs. The proximity correction process consists of measuring several generic test patterns processed on a wafer and constructing a multilevel lookup table from the measured data.
An object of the present invention is to provide for a method and apparatus for application of proximity correction to a desired pattern. The present invention is a method and apparatus for applying proximity correction to a piece of a mask pattern, by segmenting the piece into a plurality of segments, and applying proximity correction to a first segment taking into consideration the other segments of the piece.
These and other aspects, features, and advantages of the present invention will be apparent to those persons having ordinary skilled in the art to which the present invention relates from the foregoing description and the accompanying drawings.